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| INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC * The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF40245B buffers Octal bus transceiver with 3-state outputs Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification Octal bus transceiver with 3-state outputs DESCRIPTION The HEF40245B is an octal bus transmitter/receiver designed for 8-line asynchronous, 2-way data communication between data buses. It features output stages with high current output capability suitable for driving highly capacitive loads. The direction input (DR) controls transmission of data from bus A to bus B, or bus B to bus A, depending on its logic level. The 3-state outputs are controlled by the enable input EO. A HIGH on EO causes the outputs to assume a high impedance OFF-state. The device also features hysteresis on all inputs to improve noise immunity. Schmitt-trigger action in the inputs makes the circuit highly tolerant to slower input rise and fall times. The HEF40245B is pin and functionally compatible with the TTL `245' device. PINNING A0 to A7 B0 to B7 DR EO HEF40245B buffers data input/output data input/output direction input output enable input (active LOW) HEF40245BP(N): 20-lead DIL; plastic (SOT146-1) HEF40245BD(F): 20-lead DIL; ceramic (cerdip) (SOT152) HEF40245BT(D): 20-lead SO; plastic (SOT163-1) ( ): Package Designator North America Fig.2 Logic diagram; for functional diagram see Fig.3. FAMILY DATA, IDD LIMITS category buffers See Family Specifications. Fig.1 Pinning diagram. January 1995 2 Philips Semiconductors Product specification Octal bus transceiver with 3-state outputs FUNCTION TABLE INPUTS EO L L H Notes DR L H X HEF40245B buffers INPUTS/OUTPUTS An A=B input Z Bn input B=A Z 1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state is immaterial Z = high impedance OFF-state (1) P-channel MOS transistor conducting. (2) P-channel MOS transistor and bipolar n-p-n transistor conducting. Fig.4 Typical output source current characteristic. Fig.3 Functional diagram. Fig.5 Schematic diagram of output stage. January 1995 3 Philips Semiconductors Product specification Octal bus transceiver with 3-state outputs RATINGS Limiting values in accordance with the Absolute Maximum System (IEC 134) See Family Specifications, except for: D.C. current into any input D.C. source or sink current into any output D.C. current into the supply terminals DC CHARACTERISTICS VSS = 0 V VDD V VOH V VOL V SYMBOL Tamb (C) -40 MIN. Output current HIGH Output current HIGH Output current LOW Hysteresis voltage (any input) 3-state input/output leakage current pins An or Bn Note 1. Relevant output in OFF-state; An at VSS or VDD; Bn at VSS or VDD. 15 IOZ(1) - 1,6 - - 1,6 5 10 15 5 10 15 5 10 15 5 10 15 VH 4,6 9,5 13,5 3,6 8,4 13,2 0,4 0,5 1,5 IOL -IOH -IOH 0,75 1,85 14,5 9,3 14,4 19,5 2,9 9,5 30,0 MAX. MIN. 0,6 1,5 15 10 15 20 2,3 7,6 25 + 25 TYP. 1,2 3,0 50 24 46 62 5,4 17 45 220 250 320 MAX. II IO I max. max. max. HEF40245B buffers 10 mA 25 mA 100 mA + 85 MIN. 0,45 1,1 15,5 10,7 15,0 19,8 1,75 5,50 19,0 MAX. mA mA mA mA mA mA mA mA mA mV mV mV - 12 A January 1995 4 Philips Semiconductors Product specification Octal bus transceiver with 3-state outputs AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns VDD V Propagation delays An Bn HIGH to LOW An Bn LOW to HIGH Output transition times HIGH to LOW LOW to HIGH 3-state propagation delays Output disable times EO An, Bn HIGH 5 10 15 5 LOW Output enable times EO An, Bn HIGH 5 10 15 5 LOW 10 15 tPZL tPZH 100 45 35 115 55 45 200 90 70 230 110 90 ns ns ns ns ns ns 10 15 tPLZ tPHZ 100 50 40 100 60 50 200 100 80 200 120 100 ns ns ns ns ns ns 5 10 15 5 10 15 5 10 15 5 10 15 tTLH tTHL tPLH tPHL 95 40 30 85 40 30 40 20 15 30 20 15 190 80 60 170 80 60 80 40 30 60 40 30 ns ns ns ns ns ns ns ns ns ns ns ns see Fig.6 SYMBOL MIN. TYP. MAX. HEF40245B buffers TYPICAL EXTRAPOLATION FORMULA 83 ns + (0,24 ns/pF) CL 35 ns + (0,10 ns/pF) CL 26 ns + (0,07 ns/pF) CL 82 ns + (0,06 ns/pF) CL 38 ns + (0,03 ns/pF) CL 29 ns + (0,02 ns/pF) CL ALL BUFFERS SWITCHING Dynamic power dissipation per package (P) VDD V 5 10 15 TYPICAL FORMULA FOR P (W) 4 250 fi + (foCL) x VDD2 17 000 fi + (foCL) x VDD 46 000 fi + (foCL) x VDD 2 2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) (foCL) = sum of outputs VDD = supply voltage (V) January 1995 5 Philips Semiconductors Product specification Octal bus transceiver with 3-state outputs HEF40245B buffers tTLH - - - - tTHL Fig.6 Output transition times as a function of the load capacitance. January 1995 6 |
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